Binary digital signals obtained by converting analog signals output from a resolver to a digital format (RD conversion, comparate) and other digital signals representing a waveform by fluctuation of the signal level (potential etc.) contain noise due to various factors mixed in them.
FIG. 7A to FIG. 7E are diagrams explaining the effects of chattering upon a zero cross of an analog signal and a digital signal. FIG. 7A is a diagram showing 1 cycle's worth of an analog signal Sga1. The abscissa indicates the time (phase), while the ordinate indicates the signal level. Further, FIG. 7B is a diagram showing a digital signal Sgd1 obtained by converting the analog signal Sga1 of FIG. 7A to a digital format. The abscissa indicates the time (phase), while the ordinate indicates the signal level.
As shown in FIG. 7A, the analog signal Sga1 is identified in its period and phase based on a zero cross point P1 crossing a signal level forming the standard (crossing zero), that is, the reference level Vo. Further, as shown in FIG. 7B, the position of the zero cross point of the analog signal Sga1 corresponds to the position of a rising edge Ed1 (or trailing edge) of the digital signal Sgd1.
FIG. 7C is an enlarged diagram of a region R1 of FIG. 7A, that is, an enlarged diagram near the zero cross point P1, while FIG. 7D is an enlarged diagram of a region R2 of FIG. 7B, that is, an enlarged diagram near the rising edge Ed1. Note that, in FIG. 7D, a clock signal Sgc1 is shown as well.
When viewing this macroscopically as in FIG. 7A and FIG. 7B, the analog signal Sga1 crosses zero at one point, while the digital signal Sgd1 has one rising edge Ed1. However, when viewing this microscopically as in FIG. 7C, due to chattering, the analog signal Sga1 crosses zero at a plurality of points (zero cross points P′1 to P′3). Further, as shown in FIG. 7D, if the period of the chattering is the period of the clock signal Sgc or more, the digital signal Sgd1 has a plurality of rising edges Ed′1 and Ed′2.
FIG. 7E is a diagram explaining the effect of the chattering upon phase measurement and shows a binary digital signal Sgd3 obtained by converting a plurality of cycles' worth of the analog signal Sga1 to a digital format and a reference signal Sgd2 compared with the digital signal Sgd3. The abscissa indicates the time (phase), while the ordinate indicates the signal level.
As shown at the left side of FIG. 7E on the page, when one rising edge should be generated in the digital signal Sgd3 corresponding to a rising edge Ed11 of the reference signal Sgd2, yet a plurality of rising edges Ed3 and Ed4 are generated due to chattering, the phase difference of the digital signal Sgd3 of the reference signal Sgd2 from the edge Ed11 will fluctuate (suffer from error) by exactly the phase difference between the rising edges Ed3 and Ed4.
Further, as shown at the right side of FIG. 7E on the page, if a rising edge Ed6 is generated in the digital signal Sgd3 corresponding to a rising edge Ed12 of the reference signal Sgd2, a rising edge Ed5 will sometimes end up being generated due to chattering near a trailing edge of a half of a cycle before that rising edge Ed6. In this case, when the phase difference between the rising edge Ed12 and the rising edge Ed6 should be detected, the phase difference between the rising edge Ed12 and the rising edge Ed5 is liable to be erroneously detected and an error of half of a cycle is liable to occur.
In order to solve such a problem, the technique using a hysteresis comparator is known (for example, Patent Document 1). In this technique, as shown in FIG. 7C, once the signal level of the analog signal Sga1 falls below the reference level V0 (crosses zero at the zero cross point P′1), when the signal level of the analog signal Sga1 exceeds a hysteresis level Vh, the next zero down cross will be detected by assuming that the analog signal Sga1 has crossed zero upward so as to thereby to remove the effect of chattering.
Note that, although not concerning the technique of removing the effect of noise exerted upon the zero cross, in a system judging a combustion state of an internal combustion engine by detection of current flowing between electrodes of a spark plug, the technique of judging the effect of smoke upon the current flowing between electrodes of the spark plug based on the time during which the current flowing between electrodes of the spark plug exceeds a predetermined level or the like is known (Patent Documents 2 and 3).    Patent Document 1: Japanese Patent Publication (A) No. 2004-12168    Patent Document 2: Japanese Patent Publication (A) No. 2004-239085    Patent Document 3: Japanese Patent Publication (A) No. 11-50941